Clock Jitter Eliminator GX7044 Compatible with HMC7044

The GX7044 is an HMC7044-compatible, high-performance, dual-loop integer and fractional divider jitter attenuator that performs frequency conversion, selects a reference signal, and generates an ultra-low phase noise clock to be supplied to high-speed data converters with parallel or serial (JESD204B) interface. The GX7044 provides 14 low-noise, configurable outputs that can be flexibly interfaced to many different devices in an RF transceiver system, such as data converters, intrinsic oscillators, transmit/receive modules, FPGAs, and digital front-end (DFE) ASICs.

The GX7044 generates up to 7 pairs of DCLKs and SYSREFs, meeting JESD204B interface requirements. The device offers excellent crosstalk, frequency isolation, and spurious performance, and supports both single-ended and differential output frequencies.The DCLK and SYSREF clock outputs can be configured for different output signal standards such as CML, LVDS, LVPECL, and LVCMOS.

Key Performance:

- Supports JEDEC JESD204B.

- Ultra-low RMS jitter

  48fs RMS Jitter (12kHz to 20MHz) @2457.6M

  Bottom Noise: -153dBc/Hz@2457.6MHz

- PLL2 provides up to 14 differential clocks

  Up to 7 SYSREF clocks

  Maximum clock output frequency 3.2GHz

  Supports LVPECL, LVDS, CML and other output interfaces.

- Supports up to 2 buffered voltage controlled oscillator (VCXO) outputs.

- Loss of Signal (LOS) detection and no-interrupt reference switching

- 4 GPIO alarm/status indicators

- Supports external VCO inputs up to 3200MHz

- Operating temperature: -40°C to 85°C

- Operating Voltage: 3.15V to 3.45V

- QFN-68 package

Application Scenarios: JESD204B Clock Generation, Wireless Infrastructure (Multi-Carrier GSM, LTE, W-CDMA), Data Converter Clock, Microwave Baseband Card, Phased Array Reference Distribution